1. Field of the Invention
The present invention generally relates to semiconductor devices and, more particularly, to a semiconductor device which is encapsulated together with other semiconductor devices before being divided into individual semiconductor devices and is tested by being positioned in a test apparatus by image recognition.
2. Description of the Related Art
A semiconductor device formed by packaging a semiconductor chip is subjected to a semiconductor test for checking its operation at the end of its manufacturing process. When such a semiconductor device is loaded on a semiconductor test apparatus in the test process, the semiconductor device is positioned in the semiconductor test apparatus by referring to an outer configuration of the semiconductor device. Such a positioning operation is performed by a handling device. That is, the semiconductor device subjected to the test is positioned by referring to the outer configuration of the package when mounting the semiconductor device to a socket of the test apparatus.
In recent years, miniaturization of semiconductor chips has greatly advanced, and, therefore, the package size of the semiconductor devices has also been reduced. Accordingly, when the handling device is used for positioning the semiconductor device by referring to an outer configuration, the handling device must be altered every time the package size is changed.
Additionally, semiconductor chips having a package size the same as the size of the semiconductor chip have been increased. Thus, an altering jig must be prepared for each kind of semiconductor chip. Additionally, even when the same kind of semiconductor chip is used, the handling device must be altered each time the size of the semiconductor chip is reduced. Accordingly, a cost of the alteration of the handling device is markedly increased.
Additionally, in association with miniaturization of the semiconductor chips, the pitch of the electrodes of a semiconductor device has been reduced. Accordingly, in the method in which the positioning is performed by referring to an outer configuration of the semiconductor device, a desired accuracy of positioning may not be achieved.
Under the above-mentioned circumstances, it has been suggested to test a plurality of semiconductor devices in a state in which the semiconductor chips are packaged in an integrally connected state. That is, a plurality of semiconductor devices formed on a wafer are cut out in an integral form, and are packaged simultaneously so as to form a plurality of semiconductor devices at the same time. In this case, an outer configuration of the semiconductor device can be standardized in a certain degree.
Additionally, it has been suggested to position the terminals of the semiconductor device relative to the socket (or probe) of the test apparatus by a method using image recognition instead of the method using an outer configuration of the semiconductor device as a reference. However, the method using image recognition is not suitable for a case in which a large number of semiconductor devices are tested in a single test process. In a case of testing semiconductor memory devices, 32 to 64 pieces of semiconductor devices are tested in a single test process. Considering a test cost, it is not practical to position each of such a large number of semiconductor devices on an individual device basis by using the method using image recognition. That is, the test apparatus must be provided with 32 to 64 image recognition devices and position correcting mechanisms that can deal with the respective image recognition devices, thereby increasing the size and complexity of the test apparatus.
In this case, the number of image recognition devices and the position correcting mechanisms provided in the handling device can be reduced by forming a plurality of memory chips in an accurately connected state and testing the plurality of memory chips while positioning the memory chips by using the image recognition instead of testing after being divided into individual memory chips.
As an example of the above-mentioned method, it is suggested to test the semiconductor chips formed on a wafer before being cut out into individual memory devices. That is, a plurality of semiconductor devices that are encapsulated in a wafer state, that is, a plurality of semiconductor devices packaged in a wafer level are subjected to a test before being divided into individual semiconductor devices. Alternatively, a plurality of semiconductor devices are cut out in integral form, and are subjected to a test. In such a case, a wafer prober (image recognition apparatus) corresponding to the integrated form of the plurality of semiconductor devices must be prepared and attached to the handling device. Alternatively, a position recognition device may be provided to the handling device instead of the wafer prober.
However, considering a cost spent on the handling device, it may be an optimum method to test the wafer-level packaged semiconductor devices in the wafer state.
In a so-called bear wafer test in which semiconductor chips are tested in a wafer state, a wafer prober is used. When the wafer-level packaged semiconductor chips are recognized by a conventional wafer prober, there are problems A) through D) as described below. In the following description, the problems are related to a case in which chip size package (CSP) semiconductor devices are used as the wafer-level packaged semiconductor devices.
A) It is difficult to recognize the position of each CSP by the recognizing device of the prober.
A-1) It is difficult to directly recognize the terminals of a semiconductor device.
a) Each of the terminals provided in the CSP is larger than an electrode pad formed on the semiconductor chip. Accordingly, the terminal of the CSP cannot be covered by the recognition area or range of a regular prober, and, thereby, it is difficult to recognize the terminal of the CSP.
b) It is difficult to recognize a terminal having a spherical shape such as a solder ball which is a typical terminal provided to the CSP. That is, since such a spherical terminal lacks a flat part, it is difficult to bring the terminal into focus.
c) Since the height of the terminals vary in a large range (about 50 μm), the terminals are not appropriate for a reference of alignment.
A-2) There is no mark for recognition other than a terminal.
There is no mark on the surface of the CSP, which mark is positioned at a known distance from a terminal.
A-3) There is a limitation with respect to a cost to provide a mark and an accuracy of positioning of the mark when the mark is provided on the surface of the CSP for recognition of position.
As a means for providing a position recognition mark on the surface of the CSP, there is a method to provide a mark by a stamp. However, it is difficult to provide the mark at a predetermined position relative to electrodes provided on the surface of the CSP with a high accuracy. Additionally, since the stamp process is added, a manufacturing cost is increased.
A-4) A cost is increased when the recognition area or range of the prober is enlarged so as to recognize a large terminal.
A description will be given of a method for recognizing a mark by a conventional wafer prober.
The maximum recognition area or range of an alignment mark recognition apparatus provided to a conventional prober is in the rage of 200 μm to 300 μm Generally, the recognition area is defined as a square having a side of about 200 μm. If the size of the mark to be recognized is less than ½ of the recognition area or range, a high recognition rate can be achieved. That is, if the size of the mark is less that ½ of the recognition area or range, the entire mark is within the recognition area or range even when an edge of the mark is at the center of the recognition area or range. Thus, a high recognition rate can be achieved.
The conventional wafer prober is configured to recognize an electrode pad provided on a semiconductor chip. The electrode pad generally has a square shape having a side of about 100 μm. Accordingly, the recognition area or range of the recognition apparatus of the conventional prober has a square shape having a side of about 200 μm.
As a method for recognizing the electrode pad, a pattern matching method is used. Generally, the recognition area or range of 200 μm-square is divided into 16 square areas each having a side of 50 μm so that a comparison is performed with a reference pattern on an individual divided-area basis.
If the shape of the mark does not vary, an arbitrary shape including a circle can be used. However, if the shape of the mark varies, for example, if there is a broken part in the outer configuration of the mark, a circle mark tends to be erroneously recognized as a different shape. That is, since a circular shape provides a uniform change in the entire outer configuration, it is difficult to find a feature thereof. Accordingly, if there is an imperfect part, the circular shape may be recognized as a different shape. On the other hand, a shape including a straight part can be easily recognized even if there is a partially broken part since the straight part can be easily recognized as a whole. Thus, a recognition rate of a shape having a straight part is high. Additionally, a shape having an edge (corner) can be easily recognized since the edge serves as an inflection point.
B) A probe provided in a probe card of the CSP cannot be recognized by a conventional prober. (The probe card is a card-like member provided with proves which are positioned to contact electrode terminals of the CSP to be tested. The probe card is changed for each CSP to be tested.)
The reason is the same as the reason mentioned in the above item A). That is, the end of the probe provided in the probe card for the CSP is larger than the recognition area or range of the probe recognition apparatus provided in the prober. The diameter of the end of the probe provided in the conventional probe card is normally less than 100 μm. On the other hand, the diameter of the terminal (solder ball) of the CSP is about 400 μm, which cannot be entirely covered by the recognition area or range of the probe recognition apparatus.
C) The wafer on which the CSPs are formed is more difficult to be fixed by suction than a wafer on which the conventional semiconductor chips are formed.
In a case of a plastic mold CSP, the thermal expansion rate of the seal resin is higher than that of the wafer (silicon (Si)). Accordingly, when the wafer returns to a room temperature after being molded at a high temperature, the wafer may deform or warp in a convex shape projecting on the wafer side since the amount of compression of the seal resin is greater than that of the wafer. The deformation becomes particularly large when the thickness of the wafer is small, thereby preventing the wafer from being fixed onto a vacuum chuck table.
D) When there is a burr on the seal resin in the wafer state, the burr may fall off during handing by the handling device. The burrs may accumulate within the handling device.